View HT82A836R_4721212.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT82A836R usb audio mcu rev. 1.10 1 august 5, 2011 general description the HT82A836R is an 8-bit high-performance risc microcontroller designed for usb phone product appli - cations. to ensure a high level of functional integration for usb phone applications, this 8-bit microcontroller in - cludes important features such as 16-bit pcm a/d con - verter, usb transceiver, serial interface engine, audio class processing unit, law compander, 6-channel 12-bit adc, 2-channel pwm and fifo. the dac in the HT82A836R operates at a sampling rate of 48khz/8khz and the 16-bit pcm adc operates at frequency of 8khz/16khz for the microphone input, with the options selected using software. the integrated dac also includes a digitally programmable gain ampli - fier with a range of 32db to +6db. the digital gain range of the adc input is from 0db to 19.5db. features usb 2.0 full speed compatible usb spec v1.1 full speed operation and usb audio device class spec v1.0 operating voltage at f sys = 6m/12mhz: 3.3v~5.5v low voltage reset function embedded high-performance 16-bit pcm adc integrated digital pga programmable gain ampli - fier 48khz/8khz sampling rate for audio playback se - lected by software 8khz/16khz audio recording sampling rate selected by software embedded class ab power amplifier for speaker driv - ing embedded high performance 16-bit audio dac audio playback digital volume control 5 endpoints supported including endpoint 0 supports 1 control, 2 interrupts and 2 isochronous transfers two hardware implemented isochronous transfers total fifo size: 496 bytes 8, 8, 384, 64, 32 for ep0~ep4 8192 16 program memory 352 8 data memory in two banks programmable frequency divider function integrated spi hardware interface port a wake-up on rising or falling transitions 6-channel 12-bit a/d converter 2-channel pwm function law compander power-down function and wake-up reduce power consumption up to of 44 bidirectional i/o lines dual 16-bit programmable timer/event counters with overflow interrupts watchdog timer 16-level subroutine nesting bit manipulation instruction 15-bit table read instruction 63 powerful instructions all instructions executed within one or two machine cycles low voltage reset function (3.0v 0.3v) 80-pin lqfp (10mm 10mm) package type technical document application note ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment HT82A836R rev. 1.10 2 august 5, 2011

! "

#

$ % & ' & ( ) ! # ! * !
&

! (
+ !
)
(
,
+ - ) . #
& # #
* ) / (
0
) ( (
0

! ! # ! "

1 2 1 1 3 1 1 1 4 1 5 1 5 4 1 3 2 ' 6 7 5 4 1 3 2 ' 6 5 7 5 5 5 5 4 5 1 5 3 5 5 2 5 ' 5 6 4 7 4 4 5 4 4 4 1 4 3 4 4 2 4 ' 4 6 1 7 ' 7 2 6 2 ' 2 2 2 2 3 2 1 2 4 2 5 2 2 7 6 ' 2 3 1 4 5 7 3 6 3 ' 3 2 3 3 3 3 1 3 4 3 5 3 3 7 1 6 1 ' $ * % ) ) 5 % ) ) / ( ) # * ) ( ! 8 ( 9 % % 1 9 3 9 1 9 4 9 5 9 9 7 % ) ) 1 % 4 % &
0 % ( : ( ) ! ) ! ( ; 7 ; ; 5 ; 4 ; 1 ; 3 ; ; 2 ( 9 % ) ) 5 7 5 4 1 3 2 % 5 ! 7 / < ! # & 7 ! 5 # & ! 4 ! 1 ) ! 3 ) ( ! ) ! ) ! 2 ) ! = % ) ) 4 / 7 / / 5 / 4 / 1 / 3 / / 2 # 7 # % ) ) 4 & ; ) ; % * ) / 9 * ) / % 4 4 % ) ) 4 5 7 2 3 1 4 5 7 % 5 & *
pin description pin name i/o configuration option description rout o right driver analog output lout o left driver analog output avss4 12-bit adc negative power supply, ground avss3 pcm adc negative power supply, ground avss2 audio power amplifier negative power supply, ground avss1 audio dac negative power supply, ground bias a capacitor should be connected to ground to increase half-supply stability music_in i power amplifier input signal source if register bit selw= 1 . the analog signal input will amplify by the power amp then output to rout and lout at the same time. avdd4 12-bit adc positive power supply avdd3 pcm adc positive power supply avdd2 audio power amplifier positive power supply avdd1 audio dac positive power supply an0~an5 i 12-bit adc analog inputs vagref i pcm adc analog ground reference voltage (should left open or connected by a bypass capacitor (ex:100pf) to ground) vag o pcm adc analog ground voltage (should connected by a bypass capacitor (ex:10 f) to ground) ti+ i op amp non-inverting input ti- i op amp inverting input tg o op amp gain setting output pwm0~pwm1 o pwm outputs pa0~pa7 i/o pull-high wake-up nmos/cmos output bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. the output structure can be either nmos or cmos types determined via configuration option. pb0~pb7 i/o pull-high wake-up bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. pc0/bz pc1/tmr0 pc2/tmr1 pc3 pc4/sdo pc5/sdi pc6/scs pc7/sck i/o pull-high wake-up bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. pin pc0 is shared with the buzzer pin bz. pins pc1/pc2 are shared with timer input pins tmr0/tmr1. pins pc4/ pc5 are shared with serial interface pins sdo/sdi. pin pc6 is shared with the serial interface slave select pin. pin pc7 is shared with the serial interface clock signal. pd0~pd7 i/o pull-high wake-up bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. HT82A836R rev. 1.10 3 august 5, 2011
pin name i/o configuration option description pe0~pe6 pe7/int i/o pull-high wake-up bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. pe7 is shared with external interrupt input int . pf0~pf3 i/o pull-high wake-up bidirectional 4-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. dvdd2 positive digital power supply dvss2 negative digital & i/o power supply, ground dvdd1 positive digital power supply dvss1 negative digital power supply, ground osci osco i o osci, osco are connected to an 6mhz or 12mhz crystal/resonator, determined by software instructions, for the internal system clock. reset i schmitt trigger reset input, active low usbdn i/o usbd- line usbdp i/o usbd+ line v33o o 3.3v regulator output absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3.3 5.0 5.5 v i dd1 operating current 5v no load, f sys =12mhz adc on, dac on 12 ma i dd2 operating current 5v no load, f sys =12mhz adc off, dac off 8 ma i sus suspend current 5v no load, system halt, usb transceiver and 3.3v regulator on 330 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (reset ) 0 0.4v dd v v ih2 input high voltage (reset ) 0.8v dd v dd v i ol i/o port sink current 5v v ol =0.1v dd 5 ma HT82A836R rev. 1.10 4 august 5, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions i oh i/o port source current 5v v oh =0.9v dd 5 ma r ph pull-high resistance 5v 30 40 80 k
v lvr0 low voltage reset 5v 2.7 3.0 3.3 v v v33o 3.3v regulator output 5v i v33o = 5ma 3.0 3.3 3.6 v dac+power amp: test condition: measurement bandwidth 20hz to 20khz, f s = 48khz. line output series capacitor with 220 f. thd+n thd+n (note) 5v 4
load 30 db 8
load 35 db snr da signal to noise ratio note1 5v 4
load 81 db 8
load 82 db dr dynamic range 5v 4
load 87 db 8
load 88 db pout output power 5v 4
load, thd=10% 400 mw/ch 8
load, thd=10% 200 mw/ch pcm adc: snr ad signal to noise ratio 5v 77 db vag reference voltage 5v 2.0 v v peak peak single frequency tone amplitude without clipping 5v 1.575 v pk note: sine wave input at 1khz, 6db a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 5v 0.4 12 mhz t wdtosc watchdog oscillator period 5v 100 s t res reset low pulse width 1 s t sst system start-up timer period 1024 *t sys t int interrupt pulse width 1 s t adc a/d conversion time 80 t ad t adcs a/d sampling time 32 t ad note: *t sys =1/f sys HT82A836R rev. 1.10 5 august 5, 2011
HT82A836R rev. 1.10 6 august 5, 2011 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from a crystal/resona - tor is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cy - cles, the pipelining structure of the microcontroller en - sures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call , that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is se- lected.
( - > ! ? ; @

( - > ! ?
( - > ! : ? ; @

( - > ! ?
( - > ! : 5 ? ; @

( - > ! : ? ! ! : ! : 5 ! . > )
! . ?
! . !

! . 5
! . 4
! . 1 +
system clocking and pipelining
( - ; @

( -
( - 5 +

5 4 1 3 ; $ a b # % c d 5 e f ! $ $ ; $ a ! $ d 5 e f b b 9 ; @

( - 5
( - 4
( - ; @

( -
( - 2 instruction fetching
HT82A836R rev. 1.10 7 august 5, 2011 however, it must be noted that only the lower 8 bits, known as the program counter low register, are di - rectly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 16 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer, sp, which can also neither be read from nor written to. at a subroutine call or interrupt acknowl - edge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases, which might cause unpredictable program branching. mode program counter bits b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 0000000000000 usb interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 play interrupt 0000000010000 multi function interrupt 0000000010100 record interrupt 0000000011000 skip program counter + 2 loading pcl pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc12~pc8: current program counter bits @7~@0: pcl bits #12~#0: instruction code address bits s12~s0: stack register bits
HT82A836R rev. 1.10 8 august 5, 2011 arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the device contains one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applica - tions, which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. organisation the program memory has a capacity of 8k by 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the usb interrupt. if a usb in - terrupt occurs, the program will jump to this location and begin execution if the usb interrupt is enabled and the stack is not full. location 008h this vector is used by the timer/event counter 0. if a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 00ch this vector is used by the timer/event counter 1. if a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 010h this vector is used by the play interrupt service pro - gram. if play data occurs, the program will jump to this location and begin execution if the play interrupt is en- abled and the stack is not full. location 014h this vector is used by the multi-function interrupt. if an interrupt results from a serial interface interrupt, an end of 12-bit a/d conversion cycle or an external inter- rupt, the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. location 018h this area is used by the record interrupt. if record data occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. !
) . $
"
) . $
"
5 ) . $
"
4 ) . $
"
#
+ 0 ) . ) .
/ 0 ) . 7 7 7 ! e #
7 7 ' e 7 7 / e e 7 7 5 7 e 7 7 7 e 7 7 1 e 7 7 7 7 e 7 7 7 1 e 7 7 7 ' e * ) / (
+ )

; "
!
7 (
+ )

; "
!
(
+ )
$ . +
> 5 3 , ? &
(
+ )

"
( g (
+ )
# 0 (
+ )
program memory structure
HT82A836R rev. 1.10 9 august 5, 2011 look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointers must first be setup which point to the data in the program memory which is to be read. in this device there are two table pointers, the low byte pointer, tblp and the high byte pointer, tbhp. however, the high byte pointer, tbhp, can only be used if it is enabled using configura - tion options. using both table pointers enables any area in the program memory to be addressed while if only the low byte pointer, tblp, is used then only the present page or last page can be addressed. if the configuration options do not enable the high byte pointer, then after setting up the low table pointer, tblp, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respec - tively. when these instructions are executed, the lower order table byte from the program memory will be trans - ferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the following diagram illustrates the addressing/data flow of the look-up table using the single table address pointer tblp: if the configuration options enable the high table pointer, tbhp, then this register together with the low table pointer, tblp, can be used together as a pair to point to any located in the program memory. after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of program memory using the tabrdc [m] instruction or from the last page of the program memory using the tabrdl [m] instruction. when either of these instructions are exe - cuted, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the following diagram illustrates the addressing/data flow of the look-up table using the dual table address pointers tblp and tbhp: table program example the following example shows how the table pointer and table data is defined and retrieved from the micro con - troller using the single table data pointer, tblp. this ex - ample uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 1f00h which refers to the start address of the last page within the 8k program memory of device. the table pointer is setup here to have an ini - tial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 1f06h or 6locations after the start of the last page. note that the value for the table pointer is refer- enced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause er - rors if used again by the main routine. as a rule it is rec - ommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. #
!
e /
/ $ / $ e ) +
0
d f
!
e /

!
$ , /
single address pointer look-up table #
/ $ / $ e ) +
0
d f e
0

/ e e
0

dual address pointer look-up table
HT82A836R rev. 1.10 10 august 5, 2011 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 1f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 1f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 1f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : data memory the data memory is a volatile area of 8-bit wide ram in - ternal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. organisation the ram data memory is subdivided into two banks, known as bank 0 and bank 1, all of which are imple - mented in 8-bit wide ram. the bank 0 data memory is subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the bank 0 data memory is the address 00h and the last data memory address is ffh. the bank 1 data memory consists only of general purpose data memory. the start address of the bank 1 data memory is the address 40h and the last data memory address is ffh. selection of which bank is to be used is implemented using the bank pointer. instruction table location bits b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: pc12~pc8: current program counter bits tbhp register bit4~bit0 when tbhp option is enabled @7~@0: table pointer tblp bits
HT82A836R rev. 1.10 11 august 5, 2011 general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. as the general purpose data memory exists in two banks, bank 0 and bank1, it is necessary to first ensure that the bank pointer is properly set to the correct value before accessing the general purpose data memory. when the bank pointer is set to the value 00h, data from bank 0 will be accessed and when set to the value 01h data from bank 1 will be accessed. note that bank 1 must be accessed indirectly using the mem - ory pointer mp1 and the indirect addressing register iar1. special purpose data memory this area of data memory, is located in bank 0, where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers can be read from and written to but some are protected and are read only, the details of which are located under the rele - vant special function register section. note that for lo - cations that are unused, any read instruction to these addresses will return the value 00h. 7 e e / . / . 7 1 7 e data memory structure note: most of the ram data memory bits can be di - rectly manipulated using the set [m].i and clr [m].i instructions with the exception of a few dedicated bits. the ram data memory can also be accessed through the memory pointer registers mp0 and mp1. 7 7 e 7 e 7 5 e 7 4 e 7 1 e 7 3 e 7 e 7 2 e 7 ' e 7 6 e 7 e 7 / e 7 ! e 7 e 7 ; e 7 e 7 e e 5 e 4 e 1 e 3 e e 2 e ' e 6 e e / e ! e e ; e e 5 7 e 5 e 5 5 e 5 4 e 5 1 e 5 3 e 5 e 5 2 e 5 ' e 5 6 e 5 e 5 / e 5 ! e 5 e 5 ; e 5 e 4 7 e 4 e 4 5 e 4 4 e 4 1 e 4 3 e 4 e 4 2 e 4 ' e 4 6 e 4 e 4 / e 4 ! e 4 e 4 ; e 4 e 1 7 e 1 e 1 5 e 1 4 e 1 1 e 1 3 e 1 e 1 2 e 1 ' e 1 6 e 1 e 1 / e h 3 e b *
c
i 7 7 i / . 7 ) +
&

( & 7 # 7 ( & # / ! ! ! $ / $ / $ e ) ) * ) ( 9 ! 7 # & 7 e # & 7 $ # & 7 ! # & e # & $ # & ! ! / / ! ! ! ! ! ; ; ! ! ( 9 ! / e * ) ! * ) & * ! ! & ) $ $ ) ( ; ) # ( ) ! ) ; ( ( 7 ( ( 5 ( 4 ( 1 ! 8 $ ( # ( 8 $ ! 8 $ ( # ( 8 e ! 8 & 8 ! & $ ! ; & 8 # ; # ; 8 ! & $ ) / ! & ) / & & ; ! & 8 ( 9 8 $ & ; ! & 8 ( 9 8 e $ a 8 $ 8 $ $ a 8 $ 8 e $ a 8 & 8 $ $ a 8 & 8 e & ; ! & 8 8 $ & ; ! & 8 8 e & $ & e ! & ! ) & 8 = ; 8 ! & $ # ! # 7 # # ( ! * ) / 8 ) ; * ) % ! special purpose data memory structure
HT82A836R rev. 1.10 12 august 5, 2011 special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, usb port, etc., as well as external functions such as i/o data control. the location of these registers within the data memory begins at the address 00h . any unused data memory locations between these special function regis - ters and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of 00h. indirect addressing register iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can ac - cess data from both bank 0 and bank 1. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointer mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers pro - viding a convenient way with which to address and track data. when any operation to the relevant indirect ad - dressing registers is carried out, the actual address that the microcontroller is directed to, is the address speci - fied by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0 only, while mp1 and iar1 are used to access data from both bank 0 and bank 1. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory ad - dresses.
HT82A836R rev. 1.10 13 august 5, 2011 bank pointer bp the data memory is divided into two banks, known as bank 0 and bank 1. selecting the required data memory area is achieved using the bank pointer. if data in bank 0 is to be accessed, then the bp register must be loaded with the value 00 , while if data in bank 1 is to be ac - cessed, then the bp register must be loaded with the value 01. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irre - spective of the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. directly addressing the data memory will al - ways result in bank 0 being accessed irrespective of the value of the bank pointer. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh, tbhp these three special function registers are used to con - trol operation of the look-up table, which is stored in the program memory. tblp is the table low byte pointer and indicates the lowest 8-bit address location where the ta - ble data is located. tbhp is the table high byte pointer and indicates the highest bit address location where the table data is located. the tbhp high byte table pointer can only be used if its configuration option is selected. the table pointers must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, al - lowing for easy table data pointing and reading. if the tbhp configuration is enabled, then the tblp and tbhp register pair can be used together with the tabrdc instruction to point directly to any location in the program memory. tblh is the location where the higher order byte of the table data is stored after a table read data instruction has been executed. the lower or - der table data byte is transferred to a user defined loca - tion. watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra- tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi- sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - 2 7 / 7 / 7 #
7 / . 7 / . 9
c

i 7 i bank pointer
HT82A836R rev. 1.10 14 august 5, 2011 tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. interrupt control registers intc0, intc1, mfi1c these three 8-bit registers, known as the intc0, intc1 and mfi1c control the operation of the interrupts. by setting various bits within this register using standard bit manipulation instructions, the enable/disable function of the all interrupts can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the reti instruction. note in situations where other interrupts may require servicing within present interrupt service routines, the emi bit can be manually set by the program after the present inter - rupt service routine has been entered. timer/event counter registers tmrl/tmrh, tmrc the device contains two 16-bit timer/event counters. each timer/event counter has an associated register pair, known as tmr0l/tmr0h and tmr1l/tmr1h which are the locations where the timer s 16-bit value is located. each timer also has an associated control reg- ister, known as tmr0c and tmr1c which contains the setup information for the associated timer. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc, pd, pe and pf. these labeled i/o registers are mapped to specific ad - dresses within the data memory as shown in the data memory table, which are used to transfer the appropri - ate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc, pdc, pec and pfc, also mapped to spe - cific addresses with the data memory. the control regis - ter specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program ini - tialization, it is important to first setup the control regis - ters to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits using the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating spe - cific bits of the i/o control registers during normal pro - gram operation is a useful feature of these devices. % < ! ! ! " # $ ! 0 @ 0 <
0 "
0 , 0 % & $ ,
, 0
0 9 +

c
i 7 i 2 7 status register
HT82A836R rev. 1.10 15 august 5, 2011 port a wake-up control register pa_wake_ctrl this register is used to select the edge type that triggers the wake-up function on the port a pins. if the configura - tion options select some or all of the port a pins to have a wake-up function then this register can be used to se - lect either whether the active edge is a negative or posi - tive transition. only port a is allowed this selection. pulse width modulator registers pwm0, pwm1, pwmc the device 2 integrated pulse width modulators. each one has its own independent register, known as pwm0 and pwm1. the 8-bit contents of each of these registers define the duty cycle value for the modulation cycle of the corresponding pulse width modulator. the pwmc is the control register for the pwm functions and controls the mode selection and on/off function. a/d converter registers adrl, adrh, adcr, acsr the device contains a single 6-channel 12-bit a/d con - verter. the correct operation of the a/d requires the use of two data registers, a control register and a clock source register. there are two data registers, a high byte data register known as adrh, and a low byte data register known as adrl. these are the register loca- tions where the digital value is placed after the comple- tion of an analog to digital conversion cycle. the channel selection and configuration of the a/d converter is setup via the control register adcr while the a/d clock frequency is defined by the clock source register, acsr. usb registers the device contains an internal usb port which is con - trolled via several registers. these are used to setup the usb operation, the external pins, error handling etc. as this register list is too numerous to list here details can be found in the relevant usb description. pfd registers pfdc, pfdd the device contains a fully integrated programmable frequency driver otherwise known as the pfd. two registers control the overall operation of the pfd to de - termine the output frequency and the function en - able/disable. other registers the device contains several other special function reg - isters for control of various internal functions. as their functional description is too detailed to be described here their details will be provided in the relevant func - tional description section. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the microcontroller provides a maximum of 44 bidirectional input/output lines labeled with port names pa, pb, pc, pd, pe and pf. these i/o ports are mapped to the data memory with addresses as shown in the special purpose data memory table. seven of these i/o lines can be used for input and output opera - tions and one line as an input only. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains un - changed until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via configuration options and are implemented using a weak pmos transistor. port a wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is im- portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is a logical transition on one of the port a~port f pins from high to low. after a halt instruction forces the microcontroller into entering the power down mode, the device will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a~port f changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that each pin on port a~port f can be selected individually using configuration op - tions to have this wake-up feature. additionally port a pins have an additional selection allowing their wake-up function to be either negative or positive edge triggered. this option is provided using the pa_wake_ctrl reg - ister. only port a pins have this feature, the wake-up pins on the other ports are only negative edge triggered.
HT82A836R rev. 1.10 16 august 5, 2011 i/o port control registers each i/o port has its own control register pac, pbc, pcc, pdc, pec and pfc, to control the input/output configuration. with this control register, each cmos output or input with or without pull-high resistor struc - tures can be reconfigured dynamically under software control. each of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be di - rectly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the pro- gram will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. serial interface the serial interface pins sdo, sdi, scs and sck are pin-shared with the i/o pins pc4, pc5, pc6 and pc7. for applications not requiring serial interface, the pin-shared pins can be used as a normal i/o pin. external interrupt the external interrupt pin int is pin-shared with the i/o pin pe7. for applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the mfi1c register must be disabled. external timer/event counter input the external timer pins tmr0/tmr1 are pin-shared with the i/o pins pc1/pc2. if these shared pins are to be used as a timer/event counter inputs, then the timer/event counter must be configured to be in the event counter or pulse width measurement mode. this is achieved by setting the appropriate bits in the relevant timer/event counter control register. the pin must also be setup as an input by setting the ap - propriate bit in the port control register pull-high re - sistor options can also be selected via the appropriate port pull-high configuration option. if the shared pin is to be used as a normal i/o pin, then the external timer input function must be disabled, by ensuring that the corresponding timer/event counter is configured to be in the off mode or timer mode. pfd output the device contains a pfd function whose single out- put is pin-shared with pc0. the output function of this pin is chosen via software. note that the correspond- ing bit of the port control register, pcc.0, must setup the pin as an output to enable the pfd output. if the pcc port control register has setup the pin as an in - put, then the pin will function as a normal logic input with the usual pull-high option, even if the pfd config - uration option has been selected. spi interface the device contains an internal spi interface whose pins are shared with i/o pins pc4~pc7. the spi in - terface control register, sbcr, is used to determine if these pins are to be used as normal i/o pins or as spi interface pins. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. ' ( # 2 7 - 7 - 7 , .
+

- , .
+

- 5 , .
+

- 4 , .
+

- 1 , .
+

- 3 , .
+

- , .
+

- 2 , .
+

- - 5 - 4 - 1 - 3 - - 2 - @ 7 "

, , port a wake-up
HT82A836R rev. 1.10 17 august 5, 2011 programming considerations within the user program, one of the first things to con- sider is port initialisation. after a reset, all of the data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the pac, pbc, pcc, pdc, pec and pfc port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated pa, pb, pc, pd, pe and pf port data registers are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. timer/event counters the provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. the device contains two in- ternal 16-bit count-up timers each of which has three op- erating modes. the timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. there are three registers related to each of the timer/event counters, these are a pair or timer regis - ters and a control register. the register pairs tmr0l/ tmr0h and tmr1l/tmr1h contain the 16-bit timing value. writing to these register pairs places an initial starting value in the timer/event counter preload regis - ters while reading them retrieves the contents of the timer/event counter. the tmr0c and tmr1c regis - ters are the timer/event counter control registers, which define the timer options, and determines how the timers are to be used. the timer clock source can be configured to come from the internal system clock source or from an external clock on shared pin pc1/tmr0 and pc2/tmr1.

! " # $ % & ' " ( ) ' " * & + ( & ' & ( * # " , ' * % -
-

' % . ( " ' $ . . / 0 " # 1 ) ' " & ' & ( $ , 2 % " ' * (
' % . ( * # " , ' * %
1 " ) ( * , * ' * & + (
' % . ( * # " , ' * % 2 % " ' * ( & ' & ( * # " , ' * % & ' & ( " ' 3 , ' * 4 ( 2 & 5 * / $ ) ( 6 ( . 3 7 - - ( ! % (
( ! % (
( ! % (

( ! % (
( ! % (

( ! % (

( ! % (
input/output ports 2 % " ' * ( ' ( % ' * & + ( ! % 4 ( % ' 3 , ' * 4 (
. 8 5 % ' ( & ' & read/write timing
HT82A836R rev. 1.10 18 august 5, 2011 # & 7 7 ;
; "
!
#
! /
&

/ &
"
0 , (
+ $ , /
/ 0 0
7 # 7 # 7 7 9 e /
$ , /
/
; "
!
0 ) a ) 1 timer/event counter 0 structure # & ;
; "
!
#
! /
&

/ &
"
0 , (
+ $ , /
/ 0 0
# # 7 9 e /
$ , /
/
; "
!
0 ) a ) 1 timer/event counter 1 structure configuring the timer/event counter input clock source the timer/event counter s clock can originate from var - ious sources. the system clock source is used when the timer/event counter is in the timer mode or in the pulse width measurement mode. an external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on the external timer pin, tmr0 or tmr1. depending upon the condition of the t0e or t1e bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer registers tmr0h/tmr0l, tmr1l/tmr1h the timer register are special function registers located in the special purpose data memory and is the place where the actual timer values are stored. these regis - ters exist in pairs and are known as tmr0l/tmr0h and tmr1l/tmr1h. the value in these timer registers in - creases by one each time an internal clock pulse is re - ceived or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffffh at which point the timer overflows and an internal inter - rupt signal is generated. the timer value will then be re -
HT82A836R rev. 1.10 19 august 5, 2011 set with the initial preload register value and continue counting. to achieve a maximum full range count of ffffh the preload register must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload register, this data will be immedi - ately written into the actual timer register. however, if the timer/event counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the timer register the next time an overflow occurs. note that writing data to the lower byte 8-bit registers, tmr0l/tmr1l, will only put the written data into an in - ternal lower-order byte 8-bit buffer, while writing to the high byte 8-bit registers, tmr0h/tmr1h will transfer the specified data and the contents of the lower-order byte buffer into both the tmr0/1h and tmr0/1l regis - ters. the timer/event counter preload register is modi - fied by writing to the tmr0/1h registers. reading the tmr0h/tmr1h registers will latch the contents of both the tmr0h/tmr1h and the tmr0l/tmr1l counters to the destination and the lower-order byte buffer. how - ever reading the tmr0l/tmr1l will only read the con - tents of the low byte buffer. timer control register tmr0c, tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their control register, which has the name tmr0c and tmr1c. it is the timer control reg - ister together with their corresponding timer register pair that control the full operation of the timer/event coun - ter. before the timer/event counter can be used, it is essential that the timer control register pair is fully pro - grammed with the right data to ensure its correct opera - tion, a process that is normally carried out during program initialisation. to choose which of the three modes the timer/event counter is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair tm1/tm0, must be set to the required logic levels. the timer/event counter on/off bit, which is bit 4 of the timer control register and known as ton, provides the basic on/off control of the timer/event counter. setting the bit high allows the timer/event counter to run, clear - ing the bit stops it running. if the timer/event counter is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as te. &
) ! & * ) 9 +

c
i 7 i 2 ; "
!
"
;
)

b 0

7 b

; 9 # 7 # 7
; "
!
! ;
b

7 b
+
#
)

# 7 7 # 7 7 7
"

"

+
,

#

"
;
)

b

c + 0

7 b 0

c +

9 +

c
i 7 i timer/event counter 0/1 control register
HT82A836R rev. 1.10 20 august 5, 2011 configuring the timer mode in this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. to operate in this mode, bits tm1 and tm0 of the tmrc register must be set to 1 and 0 respectively. in this mode, the internal clock is used as the timer clock. the input clock frequency to the timer is f sys /4. the timer-on bit, ton, must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. if the timer interrupt is enabled, an in - terrupt signal will also be generated. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the timer/event counter. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value. in this mode the external timer pin is used as the timer/event counter clock source. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, which is bit 3 of the timer control reg- ister, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the coun- ter will increment each time the external timer pin re- ceives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pin. to operate in this mode, the operating mode select bit pair in the timer control register must be set to the correct value. in this mode the internal clock, f sys /4, is used as the timer/event counter clock. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin re- turns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the (

!

+
:
: 5
: 9
: 9 : timer mode timing chart
: 5 ; @

( + ; l (

!

: 4
: event counter mode timing chart
HT82A836R rev. 1.10 21 august 5, 2011 enable bit is automatically reset to zero when the exter - nal control signal on the external timer pin returns to its original level, whereas in the other two modes the en - able bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter - nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event coun- ter in the pulse width measurement mode, the second is to ensure that the port control register configures the pin as an input. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quires the use of an external pin for correct operation. as the external timer pin is pin-shared with an i/o pin, it must be configured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode se - lect bits in the timer/event counter control register, se - lect either the event counter or pulse width measurement mode. additionally the port control reg - ister bit for this pin must be set high to ensure that the pin is setup as an input. any pull-high configuration for this pins will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the f sys /4 is used as the timer clock source and is therefore synchro - nised with the overall operation of the microcontroller. in this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal in - terrupt vector. for the pulse width measurement mode, the f sys /4 clock is also used as the timer clock source but the timer will only run when the correct logic condi - tion appears on the external timer input pin. as this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a re - sult there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is config - ured to be in the event counting mode which again is an external event and not synchronised with the f sys /4 clock. when the timer/event counter is read or if data is writ - ten to the preload registers, the clock is inhibited to avoid errors, however as this may result in a counting er- ror, this should be taken into account by the program- mer. care must be taken to ensure that the timers are properly initialised before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal in- terrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer register before the timer is switched on; this is because after power-on the initial value of the timer register is unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control regis - ter. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode : : 5 : 4 : 1
; @

( + 9 > , ; l 7 ?
! . (

!

! . +

"
0

0 - pulse width measure mode timing chart
HT82A836R rev. 1.10 22 august 5, 2011 bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corresponding inter - rupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn gener - ate an interrupt signal. however irrespective of whether the timer interrupt is enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the inter - rupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; usb interrupt vector jmp usbint reti org 08h ; timer/event counter 0 interrupt vector jmp tmr0int ; jump here when timer 0 overflows : org 20h ; main program ;internal timer/event counter interrupt routine tmr0int: : ; timer/event counter 0 main program placed here : reti : : begin: ;setup timer 0 registers mov a,09bh ; setup preload value timer0 counts from this value to ffffh mov tmr0l,a; mov a,00h mov tmr0h,a; mov a,080h ; setup timer 0 control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc0,a set tmr0c.4 ; start timer 0 note mode bits must be previously setup
HT82A836R rev. 1.10 23 august 5, 2011 programmable frequency divider pfd the programmable frequency divider function, pfd, allows the generation of a user defined frequency. the clock source for the pfd is the system clock divided by 4, which after being divided by 16 is then passed through a programmable prescaler and the pfdd regis - ter allows a range of user defined frequencies to be gen - erated. overall operation of the pfd is controlled using two reg - isters, the pfdc register and the pfdd register. as the pfd output pin is pin-shared with i/o pin pc0, the pfd_io bit in the pfdc register is used to select whether the pin is to be used an a normal i/o function or to be used as a pfd output. the pfden bit is used to control the overall on/off function of the pfd, while bits pres0 and pres1 are used to select the frequency di - vision ratio of the prescaler. the pfdd register provided further division of the clock source, however this register can only be written to when the pfd function is enabled. if the pfd function is disabled, then all write operations to the pfdd register will be inhibited. when the pfd is disabled note that the pfdd register will be automati - cally cleared. the pfdd contents, the pfd must be en - abled. when the generator is disabled, the pfdd is cleared by hardware. 0 ) a ) 1 1 )

> ?

& ; ) c & ; ) 7

+ + ; 9 pfd block diagram + ) 7 9 +

c
i 7 i ,
+ 0
+
b # * ) ! ( 8 ( 9
7 b * ) /
! 7 + 0 b + 7 b ! 7 ( + 2 ) ; $ 8 ( ; 9 & ; ) 7 & ; )

b

7 b

& ; ) 7 7 & ; ) 7 7 7 " & 5 1 ' 9 +

c
i 7 i pfdc register the generated frequency of the pfd function is given by the following formula: power amplifier the selw bit in the pfdc register is used to control the power amplifier input source. the software should set selw = 1 when the power amplifier signal come from music_in, otherwise the speaker output usb audio data. + 0

l

+ 5 @ > 9 : ? c ,

9 l
"
0
+ # * j ) ; $ l 7 ) ; $ l ,
+ $ * & * # * ) ( ! 8 ( 9
HT82A836R rev. 1.10 24 august 5, 2011 interrupts interrupts are an important part of any microcontroller system. when a usb interrupt, play/record data valid in - terrupt, a timer/event counter overflow, reception of spi data, a/d interrupt or external interrupt is occurs, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device provides a usb interrupt, two inter - nal timer/event counter interrupts, a play/record data valid interrupt and a multi function interrupt. this latter multi-function interrupt represents the serial interface interrupt, a/d interrupt or the external interrupt. interrupt registers overall interrupt control, which means interrupt enabling and request flag setting, is controlled by three interrupt control registers intc0, intc1 and mfi1c which are lo - cated in the data memory. by controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a usb interrupt, a play or record data valid interrupt, a timer/event counter overflow, an spi interrupt, an a/d conversion complete interrupt or an active edge on the external interrupt pin will all generate an interrupt re- quest by setting their corresponding request flag, if their appropriate interrupt enable bit is set. when this hap- pens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corre - sponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the inter - rupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the in - terrupt occurred. the various interrupt enable bits, to - gether with their associated request flags, are shown in the following diagram with their order of priority. once an interrupt subroutine is serviced, all the other inter - rupts will be blocked, as the emi bit will be cleared auto - matically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. no. interrupt source priority vector a usb interrupt 1 04h b timer/event counter 0 overflow 2 08h c timer/event counter 1 overflow 3 0ch d play interrupt 4 10h e multi function 1 interrupt subrou - tine:serial interface interrupt, a/d interrupt, external interrupt 5 14h f record interrupt 6 18h in cases where both usb and play interrupts are en - abled and where an usb and play interrupt occurs si - multaneously, the usb interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences.
HT82A836R rev. 1.10 25 august 5, 2011 , - ) *
+ b

7 b
!
# 0
+ b

7 b
&

+ b

7 b
9 +

c
i 7 i
+

0 b "
7 b "
# 0
+

0 b "
7 b "
&

+

0 b "
7 b "
9 +

c
i 7 i 2 7 ; # ( ; $ a ( $ a & ; ! # $ a intc1 register , - )
!

> ?
+ b

7 b
!
* ) /
+ b

7 b
!

; "
!
7
+ b

7 b
!

; "
!

+ b

7 b
* ) /
+

0 b "
7 b "
(

; "
!
7

0 b "
7 b "
(

; "
!

0 b "
7 b "
9 +

c
i 7 i 2 7 ; ; ( ; # ( ; ( ; ( 7 ; 7 ( intc0 register
HT82A836R rev. 1.10 26 august 5, 2011 !

( ) &
@
+ 0 ) ( c ; ( # )
!

) 0 ,
* ) / (
+ &

* ) /
; "
!
(
+ &

7 ; * ( ; 7 ( ; # ( (
+ e $ ,
( ) & !
;
# ; ( (
+ &

$ a ; $ a ( # (
+ &

# ; # ( &
(
+ &

& ; ! & ; ! (
; "
!
(
+ &

)
(
0
(
+ &

) ( ; ) ( ( ! "

(
+ &

; ( ; @
(
+ &

; ( ; ; ( interrupt structure usb interrupt the usb interrupt will be triggered by any of the follow- ing usb events resulting in the related interrupt request flag, usbf; bit 4 of intc0, being set: a pc access of the corresponding usb fifo a usb suspend signal from the pc a usb resume signal from the pc a usb reset signal when the interrupt is enabled, the stack is not full and the interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag, usbf, and emi bits will be cleared to disable other interrupts. when the pc host accesses the HT82A836R fifo, the correspond - ing usr request bit is set, and a usb interrupt is trig - gered. in this way the user can determine which fifo has been accessed. when the interrupt has been ser - viced, the corresponding bit will be automatically cleared. when the HT82A836R receives a usb sus - pend signal from the host pc, the suspend line, bit0 of the usc register, in the HT82A836R is set and a usb interrupt is also triggered. also when the device re - ceives a resume signal from the host pc, the resume line, bit3 of the usc register, is set and a usb interrupt generated. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i or et1i, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, t0f or t1f, is set, a situation that will occur when the relevant timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter 0 overflow occurs, a subroutine call to the timer 0 inter - rupt vector at location 08h, will take place. if a timer/event counter 1 overflow occurs, a subroutine call to the timer 1 interrupt vector at location 0ch will take place. when the interrupt is serviced, the timer in - terrupt request flag, t0f or t1f, will be automatically re - set and the emi bit will be automatically cleared to disable other interrupts. play interrupt for a play interrupt to occur, the global interrupt enable bit, , and the corresponding play interrupt bit, eplai, must first be set. an actual play interrupt will take place when the play interrupt request flag, playf, is set, a sit - uation that will occur at a regular play frequency of 8khz if the play_mode bit in the mode_ctrl register is
HT82A836R rev. 1.10 27 august 5, 2011 set high. if this bit is not high, then the play interrupt fre - quency will be 48khz. when the interrupt is enabled, the stack is not full and a play interrupt occurs, a subroutine call to the play interrupt vector at location 10h, will take place. when the interrupt is serviced, the play interrupt request flag, playf, will be automatically reset and the emi bit will be automatically cleared to disable other in - terrupts. multi function interrupt an additional interrupt known as the multi-function inter - rupt is provided. unlike the other interrupts, this interrupt has no independent source, but rather is formed from three other existing interrupt sources, namely the serial interface interrupt, the a/d converter interrupt and the external interrupt. the multi-function interrupt is en - abled by setting the emf1i bit, which is bit 1 of the intc1 register. an actual multi-function interrupt will be initialised when the multi-function interrupt request flag mff1 is set, this is bit 5 of the intc1 register. when the master interrupt global bit is set, the stack is not full and the corresponding emf1i interrupt enable bit is set, a multi-function internal interrupt will be generated when either a serial interface interrupt, an a/d converter in - terrupt or an external interrupt occurs. this will create a subroutine call to its corresponding vector location 014h. when a multi-function internal interrupt occurs, the multi-function request flag mff1 will be reset and the emi bit will be cleared to disable other interrupts. however, it must be noted that the request flags from the original source of the multi-function interrupt, namely the serial interface interrupt, the a/d converter or the external interrupt will not be automatically reset and must be manually reset by the user. external interrupt the device contains an external interrupt function con - trolled by the external pin int . for an external interrupt to occur, the pin must be setup as an interrupt input pin by ensuring that the corresponding external interrupt enable bit is first set. this is bit 2 in the mfi1c register and known as eei. an external interrupt is triggered by a negative edge transition on the external interrupt pin int , after which the related interrupt request flag, eif, which is bit 6 in the mfi1c register, will be set. the inter - rupt vector for the external interrupt is the multi-function interrupt located at 014h. therefore if the multi-function and external interrupts are enabled, the stack is not full and a negative logical transition occurs on pin int ,a subroutine call to location 014h will take place. the multi-function interrupt request flag mff1 will be reset automatically and the emi bit will be cleared to disable other interrupts. the external interrupt flag will not be reset automatically and needs to be reset manually by the application program. the external interrupt pin int is pin-shared with i/o pin pe7 and can only be config - ured as external interrupt pins if the interrupt is enabled and if the pin is programmed as an input pins. a/d converter interrupt the device contains an internal a/d converter with its own interrupt function. for an a/d interrupt to occur, the corresponding a/d interrupt enable bit must be first set. this is bit 1 in the mfi1c register and known as eadi. an a/d interrupt is generated when the a/d conversion process is complete, after which the related interrupt re- quest flag, adf, which is bit 5 in the mfi1c register, will be set. the interrupt vector for the a/d interrupt is the multi-function interrupt located at 014h. therefore if the multi-function and a/d interrupt are enabled, the stack is & , * ) ! )

0

+ b

7 b
!
! "

+ b

7 b
!

@

+ b

7 b
9 +

c
i 7 i )

0

+

0 b "
7 b "
"

0 b "
7 b "
; @

+

0 b "
7 b "
9 +

c
i 7 i 2 7 ; ( ; ) ( ( ; ; ( ; ( ) ( mfi1c register
HT82A836R rev. 1.10 28 august 5, 2011 not full and the a/d conversion completes, a subroutine call to location 014h will take place. the multi-function interrupt request flag mff1 will be reset automatically and the emi bit will be cleared to disable other inter - rupts. the a/d interrupt flag will not be reset automati - cally and needs to be reset manually by the application program. serial interface interrupt the device contains an internal serial interface with its own interrupt function. for a serial interface interrupt to occur, the corresponding serial interface interrupt en - able bit must be first set. this is bit 0 in the mfi1c regis - ter and known as esii. a serial interface interrupt is generated when a data reception or transmission is complete, after which the related interrupt request flag, sif, which is bit 4 in the mfi1c register, will be set. the interrupt vector for the serial interface interrupt is the multi-function interrupt, located at 014h. therefore if the multi-function and serial interface interrupt are enabled, the stack is not full and a serial interface data reception or transmission is complete, a subroutine call to location 014h will take place. the multi-function interrupt re - quest flag mff1 will be reset automatically and the emi bit will be cleared to disable other interrupts. the serial interface interrupt flag will not be reset automatically and needs to be reset manually by the application pro- gram. record interrupt for a record interrupt to occur, the global interrupt en- able bit, emi, and the corresponding record interrupt bit, reci, must first be set. an actual record interrupt will take place when the record interrupt request flag, recf, is set, a situation that will occur when the record data is valid. when the interrupt is enabled, the stack is not full and a record interrupt occurs, a subroutine call to the record interrupt vector at location 18h, will take place. when the interrupt is serviced, the record inter - rupt request flag, recf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. if the a/d converter is powered down (ad_enb =1), pll clock disabled (pllen =1) or usb clock disabled (usbcken=0), the record interrupt also be disabled. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the con - tents of the accumulator or status register are altered by the interrupt service program, which may corrupt the de - sired control sequence, then the contents should be saved in advance. reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the reset line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to pro - ceed with normal operation after the reset line is allowed to return high. another type of reset is when the watch - dog timer overflows and resets the microcontroller. all types of reset operations result in different register con - ditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the reset reset is im - plemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad -
HT82A836R rev. 1.10 29 august 5, 2011 dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the reset pin, whose additional time delay will en - sure that the reset pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the reset line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the reset pin and a capacitor connected between vss and the reset pin will provide a suit- able external reset circuit. any wiring connected to the reset pin should be kept as short as possible to min- imize any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. res pin reset this type of reset occurs when the microcontroller is already running and the reset pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. low voltage reset lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device in - ternally. the lvr includes the following specifica - tions: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. char - acteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera- tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. & ; ) ; 7 - 7 7 . % % ) ) 7 - 7 7 . enhanced reset circuit & ; ) ; % % ) ) 7 - 7 7 . basic reset circuit & ; ) % ) )
(
&

7 - 6 % & ) power-on reset timing chart $ % & ) )
(
&

& ) low voltage reset timing chart
) )
(
&

& ) wdt time-out reset during normal operation timing chart
) )
) ) wdt time-out reset during power down timing chart & ; ) ) )
(
&

7 - 6 % 7 - 1 % & ) res reset timing chart
HT82A836R rev. 1.10 30 august 5, 2011 reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal regis - ters of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. the states of the registers are summarized in the table. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu 0000 0111 0000 0111 status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --01 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111
HT82A836R rev. 1.10 31 august 5, 2011 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pf ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu ---- 1111 ---- 1111 pfc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu ---- 1111 ---- 1111 intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu usc 1000 0000 uuxx uuuu 10xx 0000 10xx 0000 10xx uuuu 1000 0u00 1000 0u00 usr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 00uu 0000 00uu 0000 ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sies 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 setio xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 xxxx x010 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo4 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 dac_limit_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 dac_limit_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 dac _wr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pga_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00uu uuuu 00uu uuuu pfdc 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 pfdd 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 oper_mode 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu mode_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu 0000 0uuu 0000 0uuu sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu record_in_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu record_in_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datal_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
HT82A836R rev. 1.10 32 august 5, 2011 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) play_datal_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datar_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu play_datar_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu record_data_l 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu record_data_h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu adrl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu uuuu uuuu uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu u--- --uu u--- --uu pa_wake_ctrl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu pwmc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mfi1c 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 usb_state 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu usvc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 * stands for warm reset u stands for unchanged x stands for unknown stands for unimplemented oscillator the device use crystal oscillator as the system clock source. two types of crystal system clock frequencies can be selected while various clock source options for the watchdog timer are provided for maximum flexibil - ity. system crystal/ceramic oscillator for the 12mhz crystal oscillator configurations, the sim - ple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscil - lation. for the 6mhz crystal oscillator configuration the addition of two small value capacitors are required. the sysclk bit in the ucc register determines the system frequency selection. crystal c1, c2 6mhz crystal 22pf 12mhz crystal nc watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 us at 5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. ) ! ) ! ( ! 5 ! crystal/ceramic oscillator
HT82A836R rev. 1.10 33 august 5, 2011 power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mode or sleep mode. when the device enters this mode, the nor - mal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consump - tion to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requir - ing a full reset. this feature is extremely important in ap - plication areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi- nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. this also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as out - puts. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling or rising edge on port a an external falling edge on port b~port f a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual config- uration option to permit a negative (or positive) transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. each pin on can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. port a has an addition function, controlled via the pa_wake_ctrl register in the data memory, allowing either a negative or positive edge to initiate a wake-up function. any external pin wake-up will cause the system to resume execution at the in - struction following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled.
HT82A836R rev. 1.10 34 august 5, 2011 no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by two sources selected by configura - tion option: its own self contained dedicated internal wdt oscillator or f sys /4. note that if the wdt configura - tion option has been disabled, then any instruction relat - ing to its operation will result in no operation. the internal wdt oscillator has an approximate period of 65 s at a supply voltage of 5v. if selected, it is first di - vided by 256 via an 8-stage counter. note that this pe - riod can vary with vdd, temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period. a configuration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the reset pin, the second is us - ing the watchdog software instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, succes- sive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly, after the clr wdt2 instruc- tion has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. ) 5 ' + 2 7 +

) 5 7 7 7 7 ) 7 7 7 7 ) 7 7 7 7 7 &
b b 5 b 1 b ' b b 4 5 b 1 b 5 ' 9
) ) 7 7 5 4

4 7
5 +

;
! ,

9 +
7 7 watchdog timer register
HT82A836R rev. 1.10 35 august 5, 2011 ! . )
! 0 + !
+
! 0 + ! $ & ! $ & 5 ! $ & ' !
> 5 3 ? 0 ) a ) 1 5 ( ! . )
! $ & 2

' # * j ) 7 h ) 5
watchdog timer usb function the device includes a usb 1.1 interface which can be used for data application data transfer. five endpoints are included in the usb function of this device. usb interface the interface in the HT82A836R device has 5 end - points, known as ep0~ep4. endpoint 0, ep0, is used for control transfer. endpoints ep1 and ep4 are for inter - rupt transfer, while ep2 supports the isochronous out transfer. ep3 supports isochronous in transfer. a set of registers stored in the data memory is used for overall control of the usb function. these control registers in- clude, usc, usr, ucc, awr, stall, sies and misc. there are also five fifo registers with the names fifo0~fifo4. the size of each fifo is as follows:, fifo0-8 bytes, fifo1-8 bytes, fifo2-384 bytes, fifo3-32 bytes and fifo4-64 bytes, giving a total of 496 bytes. the urd bit, which is bit7 of the usc register is the usb reset signal control function definition bit. usb interface registers the usb setup, data management and endpoint control in the device is controlled via a series of registers in the data memory. usc register the usc register is the register for the overall control of the usb function. the initial status of this register is 80h. further explanation of each of the bits is given below: susp the susp bit is the usb suspend indicator bit. when this read-only bit is set to 1 by the sie, it indicates that the usb bus has entered the suspend mode. the usb interrupt is also triggered when this bit changes from low to high. rmwk the rmwk read/write bit is the usb remote wake-up command. it is set by the mcu to allow the usb host to leave the suspend mode after an external wake-up. urst the urst read/write bit is the usb reset indication bit. this bit is set and cleared by the usb sie and indi - cates a usb reset event on the usb bus. when this bit is set to 1 , this indicates that a usb reset has oc - curred and that a usb interrupt will be generated. resume the resume read only bit is used to indicate that the usb has left the suspend mode. when the usb has left the suspend mode, this read-only bit is set to 1 by the sie. when the resume bit is set by sie, an in- terrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set the usbcken bit and clear susp2 in the ucc register, to enable the sie detect function. the resume bit will be cleared when susp goes to 0 . when the mcu is detecting the susp, the condition of the re - sume bit, which will wake-up the mcu, should be noted and taken into consideration. v33c the v33c read/write bit is the control bit for the inter - nally generated 3.3v supply for the usb interface. pllen the pllen read/write bit is the control bit for the inter - nal phase locked loop function. crcfg the crcfg read/write bit is the crc error condition failure flag. the crcfg bit will be set by the hardware however the crcfg bit needs to be cleared using firmware. urd the urd read/write bit is the usb reset signal control function definition bit.
HT82A836R rev. 1.10 36 august 5, 2011 usr register the usr register is the usb endpoint interrupt status register and is used to indicate which endpoint is ac- cessed and to select the usb bus. the endpoint request flags, ep0f, ep1f, ep2f, ep3f and ep4f are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 and the usb interrupt will be generated if the usb interrupt is enabled and the stack is not full. when the active endpoint request flag is serviced, the endpoint re - quest flag has to be cleared to 0 by software. further explanation of each of the bits is given below: esp0f~esp4f the esp0f~esp4f read/write bits are set by the sie an indicate whether the associated endpoint has been accessed and a usb interrupt generated. after the in - terrupt has been serviced the bits should be cleared by the application program. ucc register the ucc register is the system clock control register and is used to select the clock that is used in the mcu. this register consists of a usb clock control bit, usbcken, a second suspend mode control bit, susp2, and a system clock selection bit, sysclk. the register also controls the endpoint selection, which is determined by bits eps0, eps1 and eps2. further explanation of each of the bits is given below: eps0~eps2 these three read/write bits are for the endpoint fifo selection. it should be noted that isochronous end- points 2 and 3 are implemented in hardware, therefore fifo2 and fifo3 cannot be read from or written to using firmware. usbcken the usbcken read/write bit enables the usb clock. susp2 the susp2 read/write bit is the second suspend bit and is used to select a power reducing function when the device is in the suspend mode. in the normal mode this bit should be cleared to zero. fsys16mhz this read/write bit is used to determine if the system clock is derived from an external oscillator or from the internal pll 16mhz clock. sysclk the sysclk read/write bit is used to determine if the system clock is either 6mhz or 12mhz. awr register the awr register is used to store the current usb de - vice address and also for control of the remote wake-up function. the initial value of the awr register is 00h . the address value extracted from the usb command must not be loaded into this register until the setup stage has finished. ) 2 7 * ) / ) +
( >
? b ) +

7 b 9 +

* ) / &

.
+ b $
"
+

7 b 9
* ) / &

( b * ) /

7 b 9

* ) / &

( >
? b * ) /
0 +

7 b 9
% 4 4 + ! b % 4 4 + 7 b % 4 4 + 0 0 $ $ ;
b $ $ 0 0 7 b $ $ ! & ! ; ! b ; 7 b 9 ; * ) / &

!
0 b * ) /

,

# ! * 7 b * ) /

# ! * * & ! & ! % 4 4 ! & ; ) * # ; * & ) & # = ) * ) $ $ ; 9 usb control register usc
HT82A836R rev. 1.10 37 august 5, 2011 7 ; + 7
; +
; + 5
; + 4
; + 1
b
7 b 9
9 +

c
i 7 i ; 4 ; 5 ; ; 7 ; + 2 ; 1 usb endpoint status register usr ) ) 2 7 ) a ) ! $ = ) a ) # e g ) * ) 5 * ) / ! = ; 9 ; ) 5 ; ) ; ) 7 ; ) 7 7 7 7 ; ) 5 7 7 7 7 ; ) 7 7 7 7 7
; + ( )

*
0
c

)

; + 7 ( ! ; + ( (
+ ; + 5 ( ( ; + 4 ( ( ( ; + 1 ( (
+ * ) / ! . ! b ! .

7 b ! .
&

,
) +
b &

+ ,
,
,
7 b !
g
9
)
! . )
b # e g $ $
7 b ) !
9 +

c
i 7 i )
! .

b # e g 7 b 5 # e g system clock control register ucc ' 2 7 * ) / &

.
+ ;

b

7 b
* ) /
"

3 1 4 5 7 = ; 9 device address register awr
HT82A836R rev. 1.10 38 august 5, 2011 stall register the stall register shows whether the corresponding endpoint has operated correctly or not. as soon as the endpoint has operated incorrectly, the related read/write bit in the stall has to be set to 1 . the stall register will be cleared by a usb reset signal and a setup token event. the initial value of the stall register is 00h. sies register the sies register is the setup register for the serial in - terface engine. further explanation of each of the bits is given below: aset the read/write aset bit is used to configure the sie to automatically change the device address to the value presently stored in the awr register. when this bit is set to 1 by, the sie will update the device address with the value stored in the awr register after the pc host has successfully read the data from the device with an in operation. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately after an address is written to the awr register. therefore in order to work properly, the pro - gram has to clear this bit after a next valid setup to - ken is received. err the read/write err bit is used to indicate that errors have occurred when the fifo is accessed. this bit is set by sie and should be cleared by the program. this bit is used for all endpoints. out the read/write out bit is used to indicate the recep - tion of an out token, except for the out zero length token. the device will clear this bit after the out data has been read. also, this bit will be cleared by the sie after the next valid setup token is received. in the read only in bit is used to indicate that the current usb receiving signal from pc host is an in token. nak this read only bit is used to indicate that the sie has transmitted a nak signal to the host in response to the pc host in or out token. 2 7 ; + 7 h 1 ) ( b ; +
7 b 9 +
*
0
c
i 7 i ) $ 4 ) $ 5 ) $ ) $ 7 ) $ 2 ) $ 1 ) $ 3 ) $ endpoint stall register stall , . 7
"

)
b * +

0 e
7 b * +
0
&

,
(

b ; 7 b 9
* .

"
b .

"
7 b 9 .

"
( 9 .
b * ) /

"
( .
7 b 9 ( .
) ( ;
9 = .
b 9 = .

7 b 9 9 = .

;
b ; 7 b 9
.
+ .
"
b ( "
7 b "
9 = .

+ . b 9 = .

+ . 7 b 9
+ . ! & ! ) ; ; & & * ( 9 9 = 2 ; # 9 ( serial interface setup register sies
HT82A836R rev. 1.10 39 august 5, 2011 crcf the crcf read/write is an error condition failure flag that includes crc, pid and no integrate token error. crcf will be set by the hardware but needs to be cleared by the firmware. eot the eot read only read only flag is the token pack - age active flag. note that this flag is active low. nmi the read/write nmi bit is the nak token interrupt mask flag. if this bit set, when the device sends a nak token to the host, the interrupt will be disabled. other - wise if this bit is cleared, when the device sends a nak token to the host, it will enter the interrupt sub - routine. misc register the misc register combines command and status to control the desired endpoint fifo action and to show the status of the desired endpoint fifo. the misc reg - ister will be cleared by a usb reset signal. further explanation of each of the bits is given below: request the read/write request, if set high, can request the fifo after the corresponding status has been set. when finished this bit must be set low. tx the read/write tx bit represents the direction and mcu access transition end. when set high, the mcu desires to write data to the fifo. after finishing, this bit must be set low before terminating the request to represent a transition end. for an mcu read opera - tion, this bit must be set low and then high after finish - ing. clear the read/write clear bit mcu is used to request a fifo clear, even if the fifo is not ready. after clearing the fifo, the usb interface will send a force_tx_err to tell the host that data under-run if the host wants to read data. iso_in_en the read/write iso_in_en bit enables the isochronous in pipe interrupt. iso_out_en the read/write iso_out_en bit enables the isochronous out pipe interrupt. setcmd the read/write setcmd bit is used to show that the data in the fifo is a setup command. the bit will re - main in the same state until the following data enters the fifo. ready the read only ready bit is used to indicate that the desired fifo is ready. len0 the read only len0 bit is used to indicate that the host has sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. & , ) ( &

b &

7 b 9

# ! *

b

7 b
!
(

b &

7 b 9

( +

+ b ;
7 b
( +

+ b ;
7 b
(
+ b )
+ 7 b 9
+ (
b &
7 b 9
7 g
+ .
b 7 + .
7 b 9 7 + .
2 ( ) 8 * 8 ; 9 7 & ; k * ; ) j ! $ ; & ( ) 8 ( 9 8 ; 9 ) ; ! # & ; a $ ; 9 7 miscellaneous register misc
HT82A836R rev. 1.10 40 august 5, 2011 setio register the setio register is used to setup the endpoints to ei - ther input or output pipe type. the data token toggle bit is also contained within this register. note that for usb definition, when the host sends a set configuration, the data pipe should send data0, about the data tog - gle, first. therefore, when the device receives a set configuration setup command, the user needs to toggle this bit as the following data will send data0 first. it is only required to set the data pipe as an input pile or out - put pile. the purpose of this function is to avoid the host sending an abnormal in or out token and disabling the endpoint. all bits are read/write. setio (27h) register, usb endpoint 1~endpoint 4 set in/out pipe register. usb_state register this register is used to indicate the error state due to se0 or se1 noise as well as the usbd- and usbd+ in - put signals. the se0 and se1 bits are set by the sie and cleared with the program. suspend wake-up remote wake-up the device includes a suspend mode. if there is no sig - nal on the usb bus for over 3ms, the device will enter a suspend mode. when this happens, the suspend bit, which is bit 0 of the usc register, will be set to 1 and a usb interrupt will be generated to indicate that the de - vice should jump to the suspend state to meet the re - quirements of the usb suspend current spec. in order to meet the requirements of the suspend current, the pro - gram should disable the usb clock by clearing the usbcken bit, which is bit3 of the ucc register, to 0. the suspend current can be further decreased by set - ting the susp2 bit, which is bit4 of the ucc register. when the resume signal is sent out by the host, the HT82A836R will be woken up the by the usb interrupt and the resume bit, which is bit 3 of the usc register, will be set. in order to make the device operate correctly, the program must set the usbcken bit and clear the susp2 bit. since the resume signal will be cleared be - fore the idle signal is sent out by the host and the sus - pend bit, will change to 0 . therefore when the mcu is detecting the suspend line, the condition of the re - sume line should be noted and taken into consideration. . , " 7 .

)
; + (
0 i i b ( + 7 b + )
; + 5 (
0 i i b ( + 7 b + )
; + 4 (
0 i i b ( + 7 b + )
; + 1 (
0 i i b ( + 7 b + *
0
2 ) ; ( 1 ) ; ( 4 ) ; ( 5 ) ; ( usb endpoint setup in/out pipe register setio . 7 *
0
c
i 7 i ) ; 7

b 9

* ) / 7 b 9

) ;

b 9

* ) / 7 b 9

* ) / + * ) / : + *
0
c
i 7 i 2 * ) / * ) / 9 ) ; ) ; 7 usb state register usb-state
HT82A836R rev. 1.10 41 august 5, 2011 the following shows the related timing of this operation: the device contains a remote wake-up function which can wake-up the usb host by sending a wake-up pulse through the rmwk bit, which is bit 1 of the usc register. once the usb host receives a wake-up signal from the device, it will send a resume signal to the device. the following shows the related timing: ) * ) ; 9 * ) / &

) * ) / 8 ( 9 ) * ) ; 9 * ) / &

) * ) / 8 ( 9 & # = # - 5 - 3 # - * ) / ! $ = / ) 2 7 * ) % ! # * ; * ) % ! 3 * ) % ! 1 * ) % ! 4 * ) % ! 5 * ) % ! * ) % ! 7 %
! / 7 h #
! b
7 b ;
usb speaker volume control register usvc result (db) usvc result (db) usvc result (db) usvc result (db) usvc 6 000_1100 2 111_1100 10 110_1100 24 101_1100 5.5 000_1011 2.5 111_1011 10.5 110_1011 25 101_1011 5 000_1010 3 111_1010 11 110_1010 26 101_1010 4.5 000_1001 3.5 111_1001 11.5 110_1001 27 101_1001 4 000_1000 4 111_1000 12 110_1000 28 101_1000 3.5 000_0111 4.5 111_0111 13 110_0111 29 101_0111 3 000_0110 5 111_0110 14 110_0110 30 101_0110 2.5 000_0101 5.5 111_0101 15 110_0101 31 101_0101 2 000_0100 6 111_0100 16 110_0100 32 101_0100 1.5 000_0011 6.5 111_0011 17 110_0011 1 000_0010 7 111_0010 18 110_0010 0.5 000_0001 7.5 111_0001 19 110_0001 0 000_0000 8 111_0000 20 110_0000 0.5 111_1111 8.5 110_1111 21 101_1111 1 111_1110 9 110_1110 22 101_1110 1.5 111_1101 9.5 110_1101 23 101_1101 speaker volume control table usb speaker volume control the speaker output volume as well as the speaker mute/un-mute function are controlled by the usb speaker volume control usvc register. the volume range can be set between a range of 6db to 32db by software. the relationship between the usvc volume control bits and the amplification or attenuation values are shown in the volume control ta - ble. the mute control will be enabled when the mute bit is low and both the dac and the power amplifier will be muted.
HT82A836R rev. 1.10 42 august 5, 2011 fifo registers registers r/w power-on function fifo0~ fifo4 r/w xxh epi accessing register epsx bits in the ucc register. (i = 0~4). when an end - point is disabled, the corresponding accessing register should be disabled. fifo0~fifo4 (28h~2ch) usb endpoint accessing registers definitions dac limit registers the dac_limit_l and dac_limit_h registers are used to define the 16-bit dac output limits. the values in the dac_limit_l and dac_limit_h registers are unsigned values. if the 16-bit data from the host exceeds that of the range defined by the two dac_limit_l and dac_limit_h registers then the output digital code to dac will be clamped within these register values. dac_limit_l dac output limit low byte dac_limit_h dac output limit high byte example to set the dac output limit values: ;----------------------------------------------------------- ; set dac limit value=ff00h ;----------------------------------------------------------- clr [02dh] ; set dac limit low byte=00h set [02eh] ; set dac limit high byte=ffh ;----------------------------------------------------------- in order to prevent a popping noise from the speaker output, the power amplifier should output a value of v dd /2, which means a value of 8000h should be sent to the dac during the initial power on state. generating a pulse on the dac_wr_trig bit will write the values into the dac. if the dac_wr_trig, bit 3 of the dac_wr register, is already high then clearing the dac_wr_trig bit, will write the values into the dac_limit_l and dac_limit_h registers for the dac. note: in the dac write data mode (high nibble of wdts register is 0101b), the dac_limit_l and dac_limit_h reg - isters will be the 16-bit dac input data register at the falling edge of dac_wr_trig. otherwise, these two registers are used to define the 16-bit dac output limit (repeated below). + ) 0 ' 7 &
)
b & ; ! & 8 ( 9 8 e & ; ! & 8 ( 9 8 $

7 b ! # "

0 *
0
c
i 7 i !

7 7 b $ ! *
0
c
i 7 i 2 ! 8 & 8 & ( & ; ! 8 # ; dac write and record source register dac_wr ! 8 & 8 & (

, !

"
-
HT82A836R rev. 1.10 43 august 5, 2011 rec_mode=1:writing to record_in_l register will only put the written data to an internal lower-order byte buffer (8-bit) and writing record_in_h will transfer the record_in_l and record_in_h registers content to isochronous in buffer. when record interrupt happened, firmware should write 16-bit 2 s complement value to re - cord_in_l and record_in_h (record_u_en=0) registers or write 8-bit law value to record_in_h register (record_u_en=1). rec_mode= 1 record data comes from the record_in_h and record_in_l registers rec_mode= 0 record data comes from the pcm adc (default =0) the record write data format will be controlled by bit record_u_en of oper_mode register when rec_mode= 1. the record data write format as follow: record_in_l record_in_h record_u_en= 0 pcm (low byte) pcm (high byte) record_u_en= 1 n/a law example program to eliminate pop noise: system_initial: ;----------------------------------------------------------- ; avoid pop noise ;----------------------------------------------------------- mov a,wdts mov fifo_temp,a ;save wdts value mov a,00001111b mov a,wdts mov a,01010000b orm a,wdts ;enter dac write data mode, high nibble of wdts=0101b clr [02dh] ;set dac data low byte=00h mov a,80h mov [02eh],a ;set dac data high byte=80h ;write 8000h to dac set [02fh].3 clr [02fh].3 ;----------------------------------------------------------- mov a,fifo_temp ;restore wdts value mov wdts,a ;quit dac write data mode ;-----------------------------------------------------------
HT82A836R rev. 1.10 44 august 5, 2011 digital programmable gain amplifier pga the device includes a fully integrated programmable gain amplifier, otherwise known as the pga. the pga is a digital amplifier used to amplify the 16-bit data that comes from the pcm a/d converter (rec_mode (2fh.0)=0) or from the record_in_h and re - cord_in_l (rec_mode (2fh.0)=1). the pga function is controlled using the pga_ctrl register within which there is six bits to control the gain value. this gain value ranges from 0db up to a maxi - mum of 19.5db, in steps of 0.5db, and is selected using the pga0~pga5 bits. ! # ! "

& ; ! & 8 ( 9 8 $ & ; ! & 8 ( 9 8 e & ; ! 8 # 3 h 7 * ) / 7 pga block diagram 1 0 ) 2 7 )

! 4 5 7 1 3 h 7 7 7 7 7 7 7 7 7 7 7 7 b 7 7 7 7 7 7 7 7 7 b / 7 7 - 3 b 6 - 7 6 - 3 6 - 3 b 6 - 3 ! # ! "

&

! b &

! # "

7 b 9 +
# +
#
! b 9 +
7 b # +

3 # * ; 8 # = / ! 8 & ; ) ; programmable gain amplifier control register pga_ctrl
HT82A836R rev. 1.10 45 august 5, 2011 spi serial interface the device includes a single spi serial interface. the spi interface is a full duplex serial data link, originally designed by motorola, which allows multiple devices connected to the same spi bus to communicate with each other. the devices communicate using a mas - ter/slave technique where only the single master device can initiate a data transfer. a simple four line signal bus is used for all communication. spi interface communication four lines are used for spi communication known as sdi - serial data input, sdo - serial data output, sck serial clock and scs slave select. note that the condition of the slave select line is conditioned by the csen bit in the sbcr control register. if the csen bit is high then the scs line is active while if the bit is low then the scs line will be in a floating condition. the following timing diagram depicts the basic timing protocol of the spi bus. spi registers there are two registers associated with the spi inter - face. these are the sbcr register which is the control register and the sbdr which is the data register. the sbcr register is used to setup the required setup pa- rameters for the spi bus and also used to store associ- ated operating flags, while the sbdr register is used for data storage. after power on, the contents of the sbdr register will be in an unknown condition while the sbcr register will de - fault to the condition below: cks m1 m0 sben mls csen wcol trf 011000 00 note that data written to the sbdr register will only be written to the txrx buffer, whereas data read from the sbdr register will actually be read from the register. spi bus enable/disable to enable the spi bus then csen=1 and sben=1, the sck, sdi, sdo and scs lines should all be zero, then wait for data to be written to the sbdr (txrx buffer) register. for the master mode, after data has been writ - ten to the sbdr (txrx buffer) register then transmis - sion or reception will start automatically. when all the data has been transferred the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. to disable the spi bus sck, sdi, sdo, scs floating. spi operation all communication is carried out using the 4-line inter- face for both master or slave mode. the timing diagram shows the basic operation of the bus. 2 3 1 4 5 7 ) / & > &

"
&

? # * j ) / 0 0
# * j # $ ) / # * j #
) "
) ( ) (
/ &
! . ) ! = ! . ! 5! ! 7 ) / ; 9 (
/ ) / ; 9
) / & ! $ & c ) / ; 9 ; 9 9
) / &
) / & ;

) ! ) ; 9 #
) "
! ) ; 9 ) / ; 9 c c spi block diagram
HT82A836R rev. 1.10 46 august 5, 2011 ) 2 7 ! = ) # # 7 ) / ; 9 # $ ) ! ) ; 9 ! $ & &

"
7 b 9 +

b

+ +

! / 7 b ! 0

b !

)

) ;

/ 7 b ) ! ) 0 b ;
# ) / $ ) / / 7 b $ ) / 0 0 b # ) / 0 0 )
/ ;

/ 7 b
b ;

+

+ ! ) ; 9 #
) "
/ &
/ #
c
b 0 ) ( #
c
b 0 ) ( 1 #
c
b 0 ) ( ) "

# 7 7 # 7 7 7 ! . )
)

/ 7 b 0 ) ( l 0 ) a ) 5 b 0 ) ( l 0 ) a ) spi interface control register ) ! = ) ! ) ) ( ) 2 7 3 5 1 4 4 1 5 3 7 2 2 7 3 5 1 4 4 1 5 3 7 2 ) / ; 9 l ! ) ; 9 l ,
) / & ) / ; 9 l c ! ) ; 9 l 7 ,
) / & > ( 0 +
? ) ! = spi bus timing the sben bit determines if pins pc4~pc7 are used as normal i/o pins or as spi function pins. if this bit is high then the pins will be spi function pins and here pin scs will go low if csen=1. if the bit is low then the pins will function as normal i/o pins. note that when sben=1, then any pull-high resistors connected to pins pc4~pc7 will be disconnected therefore the user hardware should ensure that external pull-high resistors are added to the spi pins if necessary. if csen = 0 then the scs pin will be in a floating state. the spi clock polarity is controlled using the sio_cpol bit in the mode_ctrl register. if sio_cpol = 1, then the rising edge will be selected. otherwise if sio_cpol = 0, the falling edge will be selected. the csen bit in the sbcr register controls the overall function of the spi interface. setting this bit high, will en - able the spi interface by allowing the scs line to be ac - tive, which can then be used to control the spi interface. if the csen bit is low, the spi interface will be disabled and the scs line will be in a floating condition and can therefore not be used for control of the spi interface. the sben bit in the sbcr register must also be high which will change the pin function from a standard i/o to an spi function pin. if in the master mode the sck line will be either high or low depending upon the clock po - larity configuration option. if in the slave mode the sck line will be in a floating condition. if sben is low then the bus will be disabled.
HT82A836R rev. 1.10 47 august 5, 2011 in the master mode the master will always generate the clock signal. the clock and data transmission will be ini - tiated after data has been written to the sbdr register. in the slave mode, the clock signal will be received from an external master device for both data transmission or reception. the following sequences show the order to be followed for data transfer in both master and slave mode: master mode: step 1. select the clock source using the cks bit in the sbcr control register. step 2. setup the m0 and m1 bits in the sbcr control register to select the master mode and the required baud rate. values of 00, 01 or 10 can be selected. step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the slave device. step 4. setup the sben bit in the sbcr control register to enable the spi interface. step 5. for write operations: write the data to the sbdr register, which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. after this goto to step 6. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7. check the trf bit or wait for an sbi serial bus interrupt. step 8. read data from the sbdr register. step 9. clear trf. step10. goto step 5. slave mode: step 1. the cks bit has a don t care value in the slave mode. step 2. setup the m0 and m1 bits to 00 to select the slave mode. the cks bit is don t care. step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the master device. step 4. setup the sben bit in the sbcr control register to enable the spi interface. step 5. for write operations: write data to the sbcr register, which will actually place the data into the txrx register, then wait for the master clock and scs signal. after this goto step 6. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7. check the trf bit or wait for an sbi serial bus interrupt. step 8. read data from the sbdr register. step 9. clear trf step10. goto step 5 sben= 1 pc4~pc7 are spi function pins (pin scs will go low if csen=1). sben= 0 pc4~pc7 are general purpose i/o port pins (default) note: (1) if sben= 1 , the pull-high resistor of pc4~pc7 will be disable. when this happens, the user should add external pull-high resistors to the spi related pins if necessary (ex: pin scs ). (2) if csen= 0 , the scs pin will enter a float - ing state. the spi cock polarity controlled by sio_cpol bit of mode_ctrl register. if sio_cpol = 1 , rising edge (clk ) will be selected. otherwise sio_cpol= 0 , fall- ing edge (clk) will be selected. error detection the wcol bit in the sbcr register is provided to indi- cate errors during data transfer. the bit is set by the se- rial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the sbdr register takes place during a data transfer operation and will prevent the write operation from continuing. the bit will be set high by the serial interface but has to be cleared by the user application program. the overall function of the wcol bit can be disabled or enabled by a sio_wcol bit of mode_ctrl register. programming considerations when the device is placed into the power down mode note that data reception and transmission will continue. the trf bit is used to generate an interrupt when the data has been transferred or received.
HT82A836R rev. 1.10 48 august 5, 2011 mode control register the mode_ctrl register is used to control dac and adc operation mode and spi function. note that the wcol and csen bits are in the sbcr register. spi usage example: spi_test: clr ucc.@ucc_sysclk ;12mhz sysclk set sio_csen ;spi chip select function enable clr sio_cpol ;falling edge change data ;master mode, sclk=f sio clr m1 clr m0 ;-------------- clr cks ;f sio =f sys /2 clr trf ;clear trf flag clr trf_int ;clear interrupt spi flag set mls ;msb shift first set csen ;chip select enable set sben ;spi enable, scs will go low if polling_mode clr esii ;spi interrupt disable ;write into write enable instruction mov a,op_wren mov sbdr,a $0: snz trf jmp $0 clr trf else set esii ;spi interrupt enable ;write into write enable instruction mov a,op_wren mov sbdr,a $0: snz trf_int ;set at spi interrupt jmp $0 clr trf_int endif & " + . 0 ) 2 7 &
8
) ( 8 ! ) ; 9 ) ( 8 ! $ ) ( 8 ! $ $ a 8 # ; 8 ; 9 / 8 & 8 ; 9 / 8 $ 8 ; 9 / ! $
0 !
! b
7 b ;

0 ! & !
! b
7 b ;

0 ! "

! b ,
, 7 b ,

0 ! #
! b ' . e g 7 b 1 ' . e g
0 ) ( ! . ! b &

7 b

0 ) ( ! $ / ! b ! $

7 b ! $

0 ) ( ! ) ; 9 / ! b ! ) ; 9

7 b ! ) ; 9

0 &

! b . e g 5 b ' . e g
0 mode control register mode_ctrl
HT82A836R rev. 1.10 49 august 5, 2011 operation mode control register the oper_mode register is used to control certain operational operational modes. the operation mode is used to control the law compander enable/disable for the speaker and microphone data. " . 0 & " + . 2 7 & ; ! & 8 * 8 ; 9 $ , ! +
! b ! +

7 b ! +

0 &
$ , ; @ +
! b ; @ +

7 b ; @ +

0 * "
$ a 8 * 8 ; 9 operation mode control register oper_mode play/record data the play and record data for the device is contained in 4 play registers and 2 record registers. the play/record inter - rupt will be activated when play/record data in the play_data or record_data registers is valid. the play_data/record_data registers will latch data until the next interrupt is generated. the dac play_data reg - ister contains an unsigned value with a range of 0~ffffh. the record_data is stored in 2 s complement format with a range of 8000h~7fffh. the update rate of the pcm adc record_data is 8khz with the record_freq bit in the mode_ctrl register is equal to 0, or 16khz if the bit is set to 1. the update rate for the play_data is 48khz, if the play_mode bit in the mode_ctrl register is equal to 0, or 8khz if the bit is equal to 1. all of the play and record registers are read only. name b7 b6 b5 b4 b3 b2 b1 b0 play_datal_l pl_d7 pl_d6 pl_d5 pl_d4 pl_d3 pl_d2 pl_d1 pl_d0 play_datal_h pl_d15 pl_d14 pl_d13 pl_d12 pl_d11 pl_d10 pl_d9 pl_d8 play_datar_l pr_d7 pr_d6 pr_d5 pr_d4 pr_d3 pr_d2 pr_d1 pr_d0 play_datar_h pr_d15 pr_d14 pr_d13 pr_d12 pr_d11 pr_d10 pr_d9 pr_d8 record_data_l r_d7 r_d6 r_d5 r_d4 r_d3 r_d2 r_d1 r_d0 record_data_h r_d15 r_d14 r_d13 r_d12 r_d11 r_d10 r_d9 r_d8 the play data format is controlled by bit play_u_en in the oper_mode register. play_datal_l play_datal_h play_datar_l play_datar_h play_u_en=0 pcm (left channel low byte) pcm (left channel high byte) pcm (right channel low byte) pcm (right channel high byte) play_u_en=1 n/a law (left channel) n/a law (right channel) the record data registers record_data_l/record_data_h will not be affected by bit record_u_en in the oper_mode register. the record data registers record_data_l/record_data_h are in pcm format.
HT82A836R rev. 1.10 50 august 5, 2011 pulse width modulator the device contains a 2 channel pulse width modulator function, more commonly known as pwm. useful for such applications such as motor speed control, the pwm function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting partic - ular values into the corresponding pwm registers. the device has two pwm outputs for which two 8-bit pwm registers are provided and are known as pwm0 and pwm1. it is in these registers, that the 8-bit value, which represents the overall duty cycle of one modula - tion cycle of the output waveform, should be placed. to increase the pwm modulation frequency, each modula - tion cycle is modulated into two or four individual modu - lation sub-sections, known as the 7+1 mode or 6+2 respectively. the mode selection is made using the pwmc register. note that it is only necessary to write the required modulation value into the corresponding pwm0 or pwm1 register, as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. for all devices, the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enables the generation of higher pwm frequencies, which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable for driving, as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however when in the 7+1 mode of operation, the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of op - eration will be f sys /64. the overall pwm output enable/disable is controlled us - ing the pwmc register which acts like an on/off switch for each pwm output. pwm modulation pwm cycle frequency pwm cycle duty f sys /64 for (6+2) bits mode f sys /128 for (7+1) bits mode f sys /256 [pwm]/256 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four in - dividual sub-cycles known as modulation cycl e0~mod - ulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which repre - sents the overall duty cycle of the pwm waveform, is di - vided into two groups. the first group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) modulation cycle i (i=0~3) i b 5 3 0 ) a ) 5 3 1 5 1 5 1 5 1 5 3 1 5 3 1 5 3 1 5 3 1 5 3 1 5 3 1 5 3 1 5 1 5 1 5 3 1 5 3 1 5 1 5 3 1 5 1 5 1 5 1 # +
b 1 0 ) a ) (6+2) pwm mode output waveform
HT82A836R rev. 1.10 51 august 5, 2011 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 7+1 pwm mode, each pwm cycle is subdivided into two indi - vidual sub-cycles known as modulation cycle 0 ~ modula - tion cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit1~bit7 is de - noted here as the dc value. the second group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two mod - ulation sub-cycles is shown in the following table. parameter ac (0~1) dc (duty cycle) modulation cycle i (i=0~1) i ! "
pulse width modulation registers for (6+2) pwm mode 0 ) a ) 5 # d # f l 7 7 d # f l 7 # d # f l 7 5 # d # f l 7 4 # # +
b 5 ' 0 ) a ) 3 7 5 ' 3 5 ' 3 5 ' 3 5 5 ' 3 7 5 ' 3 7 5 ' 3 5 ' 3 5 ' 3 7 5 ' 3 5 ' 3 5 ' 3 5 5 ' #
b 5 3 0 ) a ) (7+1) pwm mode output waveform ' & 2 6 3 * 4 & 5 2 7 ! "
! "
pulse width modulation registers for (7+1) pwm mode
HT82A836R rev. 1.10 52 august 5, 2011 pwm output control control of the two pwm outputs is achieved using the pwmc register. bits within this register control the on/off function of the individual pwm outputs as well as their chosen mode type. note than when the pwm outputs are disabled they will remain in a low state. pwm programming example the following sample program shows how the pwm outputs are setup and controlled. before use the corresponding pwm output configuration options must first be selected. mov a,64h ; setup pwm0 value of 100 decimal which is 64h mov pwm0,a clr pwmc.pwm_mod0 ; setup pin pwm0 to the 6+2 pwm mode set pwmc.pwm_en0 ; enable pwm0 output : : clr pwmc.pwm_en0 ; disable pwm0 output ' & ) # 7 + ;
b # 7 +

7 b # 7
# + ;
b # +

7 b #
*
0
c
i 7 i # 7 #
! b # 7 2 :
7 b # 7 : 5
# #
! b # 2 :
7 b # : 5
*
0
c
i 7 i 2 7 # 8 ; 9 7 # 8 ; 9 # 8 # # 8 # 7 pwm control register pwmc
HT82A836R rev. 1.10 53 august 5, 2011 analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d con - version electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the device contains a 6-channel analog to digital con - verter which can directly interface to external analog sig - nals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. the following diagram shows the overall internal struc - ture of the a/d converter, together with its associated registers. a/d converter data registers adrl, adrh for the HT82A836R device, which has a 12-bit a/d con - verter, two registers are required, a high byte register, known as adrh, and a low byte register, known as adrl, to store the 12-bit analog to digital conversion value. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. note that only the high byte register adrh utilises its full 8-bit contents. the low byte register utilises only 4 bits of its 8-bit con- tents as it contains only the lowest bit of the 12-bit con- verted value. in the following tables, d0~d11 are the a/d conversion data result bits. register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d converter data register a/d converter control register adcr to control the function and operation of the a/d con - verter, a control register known as adcr is provided. this 8-bit register defines functions such as the selec - tion of which analog channel is connected to the internal a/d converter, power on/off the a/d converter, control the start function and monitoring the a/d converter end of conversion status. one section of this register contains the bits acs2~acs0 which define the channel number. as each of the devices contains only one actual analog to digital converter circuit, each of the individual 6 analog inputs must be routed to the converter. it is the function of the acs2~acs0 bits in the adcr register to determine which analog channel is actually connected to the inter - nal a/d converter. the adcr control register also contains the pcr2~pcr0 bits which determine power on/off the a/d converter and. if the pcr2~pcr0 bits are all set to zero, then the internal a/d converter circuitry will be powered off to reduce the power consumption. any other non-zero combination on the pcr2~pcr0 bits will power-on the the a/d converter will be power on which will consume a certain amount of power. ! )
0 ) a ) 5 9 ! ) & &

! % 1 9 7 9 9 5 9 4 9 1 9 3
0

"
& $ & e &

! & 7 h ! & 5 ! ) 7 h ! ) 5 ) & ; ! / ! & &

,
0 0 ! !
)

/ ; 0 ! "
/ ! . "
& % ) ) 1 ) / a/d converter structure
HT82A836R rev. 1.10 54 august 5, 2011 + ) )

2 7 ) & ! & 5 ! & ! & 7 ! ) 5 ! ) ! ) 7 ! ) 7 7 7 7 ! ) 5 7 7 7 7
! ) 7 7 7 7 b 9 7 > & ? b 9 b 9 5 b 9 4 b 9 1 b 9 3 b *
0
c

+ ,
0 0 ! ! & 5 7 ! & 7 ! & 7 7 b "

+ ,

, ; 0 "
0 b
0 "
"
, +
7 b
0 "
"

)
"
7 7 b ) 7 b &

"

; ! / i i ; ! /
"
b "

+ ,

adcr register ) )

"

.
2 7 ; ) ! ) ! ) 7 ! ) 7 7 ! ) 7 7 7 b
. 5 b
. ' b
. 4 5 b
0
9 +

c
i 7 i

a/d converter clock source register the start bit in the adcr register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to a 1 and the analog to digital converter will be reset. it is the start bit that is used to control the overall on/off opera - tion of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is com - plete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the inter - rupts are enabled, an appropriate internal interrupt sig - nal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d inter - nal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detect - ing the end of an a/d conversion cycle. a/d converter clock source register acsr the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs1 and adcs0 bits in the acsr register. although the a/d clock source is determined by the sys - tem clock f sys , and by bits adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. a/d input pins all of the a/d analog input pins are independent analog inputs and not shared with other i/o pins. bits pcr2~pcr0 in the adcr register, not configuration options, determine whether the a/d converter is pow - ered on or powered down. the avdd4 power supply pin is used as the a/d converter reference voltage, and as such analog inputs must not be allowed to exceed this value. appropriate measures should also be taken to ensure that the avdd4 pin remains as stable and noise free as possible.
HT82A836R rev. 1.10 55 august 5, 2011 initialising the a/d converter the internal a/d converter must be initialised in a spe - cial way. each time the a/d channel selection bits are modified by the program, the a/d converter must be re-initialised. if the a/d converter is not initialised after the channel selection bits are changed, the eocb flag may have an undefined value, which may produce a false end of conversion signal. to initialise the a/d con - verter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the start bit in the adcr register must first be set high and then immediately cleared to zero. this will ensure that the eocb flag is correctly set to a high condition. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d con - version process. step 1 select the required a/d conversion clock by correctly programming bits adcs1 and adcs0 in the acsr register. step 2 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the adcr register. step 3 select a/d converter power on or power down by pro- gramming the pcr2~pcr0 bits in the adcr register. note that this step can be combined with step 2 into a single adcr register programming operation. step 4 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, in the intc0 interrupt control register must be set to 1 , the multi-function 1 inter - rupt control bit, emf1i, in the intc1 register and the a/d converter interrupt bit, eadi, in the mfi1c regis - ter must also be set to 1. step 5 the analog to digital conversion process can now be initialised by setting the start bit in the adcr regis - ter from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0. step 6 to check when the analog to digital conversion pro - cess is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the in - terrupts are enabled and the stack is not full, the pro - gram can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the following timing diagram shows graphically the vari - ous stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter func- tion is fully under the control of the application program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can con- tinue with other functions. 7 7 7 / 7 7 7 / 7 / 7 7 / ) & ; ! / ! & 5 h ! & 7 ! ) 5 h ! ) 7 ,
&

; 0 "
)

) 0 "
&

"

7 7 7 / ) 0 "
&

"

7 7 7 / "

+ ,

0 0

+ ,
+ 7 7 / 7 7 / ) 0 "
&

"

m
; 0 "
; 0 "
) &
,

0

! & 7 h ! & 5

.
0 ) a ) 5 c 0 ) a ) ' 0 ) a ) 4 5 9
b +
+
+
4 5 4 5 4 5 ! "

"

"

! ! a/d conversion timing
HT82A836R rev. 1.10 56 august 5, 2011 programming considerations when programming, special attention must be given to the a/d channel selection bits in the adcr register. this ability to reduce power by turning off the internal a/d function by clearing the a/d channel selection bits may be an important consideration in battery powered appli - cations. another important programming consideration is that when the a/d channel selection bits change value the a/d converter must be re-initialised. this is achieved by pulsing the start bit in the adcr register immediately after the channel selection bits have changed state. the exception to this is where the channel selection bits are all cleared, in which case the a/d converter is not re - quired to be re-initialised. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion for the HT82A836R. clr eadi ; disable adc interrupt mov a,00000001 b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d ; clock mov a,00100000b ; setup the adcr register to power up the a/d ; converter mov adcr,a ; and select an0 to be connected to the a/d ; converter : ; the following start signal (0-1-0) must be issued : ; within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the ; adrh register adr_buffer_h,a ; save result to user defined memory mov a,adrl ; read conversion result low byte value from the ; adrl register mov adr_buffer_l,a ; save result to user defined memory : : jmp start_conversion ; start next a/d conversion
HT82A836R rev. 1.10 57 august 5, 2011 example: using an interrupt method to detect the end of conversion for the HT82A836R. clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d ; clock mov a,00100000b ; setup the adcr register to power up the a/d ; converter mov adcr,a ; and select an0 to be connected to the a/d ; converter : ; the following start signal (0-1-0) must be issued : ; within 10 instruction cycles : start_conversion: clr adf ; clear adc interrupt request flag set emf1i ; multi function 1 interrupt enable set eadi ; enable adc interrupt set emi ; enable global interrupt clr start set start ; reset a/d clr start ; start a/d : : : ; adc interrupt service routine adc_isr: clr adf ; clear adc interrupt request flag mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrh ; read conversion result high byte value from the ; adrh register mov adr_buffer_h,a ; save result to user defined register mov a,adrl ; read conversion result low byte value from the ; adrl register mov adr_buffer_l,a ; save result to user defined register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory reti
HT82A836R rev. 1.10 58 august 5, 2011 a/d transfer function as the HT82A836R device contains a 12-bit a/d converter, their full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the voltage, this gives a single bit analog input value of v dd /4096. the following graphs show the ideal transfer function between the analog input value and the digitised output value for the a/d converters. note that to reduce the quantisation error, a 0.5 lsb offset is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the vdd level. ; e > ? ! "
&
e e 7 4 e 7 5 e 7 e 7 - 3 $ ) / 7 5 4 1 7 6 4 1 7 6 1 1 7 6 3 1 7 6 ( + %
- 3 $ ) / % 1 7 6 ideal a/d transfer function
HT82A836R rev. 1.10 59 august 5, 2011 configuration options configuration options refer to certain options within the mcu that are programmed into the otp program memory de - vice during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. all options must be defined for proper system function, the details of which are shown in the table. no. options i/o options 1 pa0~pa7: pull-high enable or disable (bit option) 2 pb0~pb7: pull-high enable or disable (bit option) 3 pc0~pc7: pull-high enable or disable (nibble option) 4 pd0~pd7: pull-high enable or disable (bit option) 5 pe0~pe7: pull-high enable or disable (bit option) 6 pf0~pf3: pull-high enable or disable (bit option) 7 pa0~pa7: wake-up enable or disable (bit option) 8 pb0~pb7: wake-up enable or disable (bit option) 9 pc0~pc7: wake-up enable or disable (nibble option) 10 pd0~pd7: wake-up enable or disable (bit option) 11 pe0~pe7: wake-up enable or disable (bit option) 12 pf0~pf3: wake-up enable or disable (bit option) 13 pa0~pa7: cmos or nmos output type (bit option) watchdog options 14 wdt: enable or disable 15 clrwdt instructions: one or two instructions 16 wdt clock source: f sys /4 or wdt oscillator lvr options 17 lvr function: enable or disable tbhp options 18 tbhp enable or disable
application circuits HT82A836R rev. 1.10 60 august 5, 2011 5 7 7 - /

% 4 % $ 4 5 4 1 ) " - 1 2 + /
1 2 + 4 4 4 4 * ) / 9 * ) / 7 % 4 4 - 3 . 7 - % % ) ) 5 7 - % * ) / * ) / : % ) ) ) 2 ) 5 ) 4 ) 1 ) 5 ) 5 5 ) 5 4 ) 5 1 ) 4 ) 4 5 ) 4 4 ) 4 1 ) 1 ) 1 5 ) 1 4 ) 1 1 ) 3 ) 3 5 ) 3 4 ) 3 1 ) ) 5 ) 4 ) 1 3 1 ; 7 ; ; 5 ; 4 ; 1 ; 3 # * ) ( ! 5 4 1 3 2 ' 6 n 7 o * 9 ! 9 ! ; $ = # * ; 8 ) ) ; $ 5 5 5 5 4 5 1 5 3 5 5 2 5 ' 5 6 4 7 4 4 5 4 4 4 1 4 3 4 4 2 4 ' 4 6 1 7 ' 7 2 6 2 ' 2 2 2 2 3 2 1 2 4 2 5 2 2 7 6 ' 2 3 1 4 5 1 2 1 1 3 1 1 1 4 1 5 1 7 3 6 3 ' 3 2 3 3 3 3 1 3 4 3 5 3 3 7 1 6 1 ' $ * % ) ) 5 % ) ) / ( ) # * ) ( ! 8 ( 9 % % 1 9 3 9 1 9 4 9 5 9 9 7 % ) ) 1 % 4 % &
0 % ( : ( ) ! ) ! ( ; 7 ; ; 5 ; 4 ; 1 ; 3 ; ; 2 ( 9 % ) ) 5 7 5 4 1 3 2 % 5 ! 7 / < ! # & 7 ! 5 # & ! 4 ! 1 ) ! 3 ) ( ! ) ! ) ! 2 ) ! = % ) ) 4 / 7 / / 5 / 4 / 1 / 3 / / 2 # 7 # % ) ) 4 & ; ) ; % * ) / 9 * ) / % 4 4 % ) ) 4 5 7 2 3 1 4 5 7 % 5 & * $ * % ) ) 5 % ) ) / ( ) # * ) ( ! 8 ( 9 % % 1 9 3 9 1 9 4 9 5 9 9 7 % ) ) 1 % 4 % &
0 % ( : ( 5 4 1 3 2 ' 6 7 5 4 1 3 2 ' 6 5 7 & ; ) ; % * ) / 9 * ) / % 4 4 % ) ) 4 5 7 2 3 1 4 5 7 % 5 & * ) ! ) ! ( ; 7 ; ; 5 ; 4 ; 1 ; 3 ; ; 2 ( 9 % ) ) 5 7 5 4 1 3 2 % 5 ! 7 / < ! # & 7 ! 5 # & ! 4 ! 1 ) ! 3 ) ( ! ) ! ) ! 2 ) ! = % ) ) 4 / 7 / / 5 / 4 / 1 / 3 / / 2 # 7 # % ) ) 4 5 # e g 5 7 7 - /

% 5 % 5 /

% ) ) 5 $ 5 $ 3 5 7 7 - /

% % $ 7 7 7 7 7 $ * & * % ) ) 5 5 4
p . )

q 3 ) 4 ) = %

5 ) 1 ) = %
( 4 ) 3 ) = #
7 4 4 7 * ) / "
$ ; 7 7 - % % ) &

7 - & ; ) ; 7 7 . % 7 - ! 7 1 2 . 9 / g g
5 4 # = % ) ) 4 7 - 7 . 7 7 . 7 7 + 7 7 . 7 7 + % % ) ) 4 7 7 - 7 . 4 - 4 . . % 4 % ) ) 4 7 : # +
5 /

% ) ) 4 5 7 7 - /

% 1 % $ 2 $ 1 5 /

% ) ) 1 $ '
HT82A836R rev. 1.10 61 august 5, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82A836R rev. 1.10 62 august 5, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82A836R rev. 1.10 63 august 5, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82A836R rev. 1.10 64 august 5, 2011
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82A836R rev. 1.10 65 august 5, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82A836R rev. 1.10 66 august 5, 2011
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82A836R rev. 1.10 67 august 5, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82A836R rev. 1.10 68 august 5, 2011
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82A836R rev. 1.10 69 august 5, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82A836R rev. 1.10 70 august 5, 2011
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82A836R rev. 1.10 71 august 5, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82A836R rev. 1.10 72 august 5, 2011
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82A836R rev. 1.10 73 august 5, 2011
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regu - lar intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 0.476 b 0.390 0.398 c 0.469 0.476 d 0.390 0.398 e 0.016 f 0.006 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 11.90 12.10 b 9.90 10.10 c 11.90 12.10 d 9.90 10.10 e 0.40 f 0.16 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 0 7 HT82A836R rev. 1.10 74 august 5, 2011 7 1 1 7 ' 7 5 7 5 / ! ; e ( q =
HT82A836R rev. 1.10 75 august 5, 2011 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

▲Up To Search▲

Price & Availability of HT82A836R

	To Download HT82A836R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .